why the hell are you simulating in a timing simulation model if you didnt need timing delay information. Look into the attachment.īrilliant! If I pass the parameter +notimingchecks in the vsim command line, the timing checks are disabled. "Show 'X' on timing violation" in the Asignment editor. I'm not sure that this will work with an external Simulator, but you can try the setting I think this option is clearly not applicable to registers in logic elements. I turned in On, but it does not have any effect in the simulation. How to set that flag to a desired value?įinally, in Quartus II, (Settings -> EDA Tool Settings -> Simulation -> More EDA Netlist Writer Settings), there is an option called "Disable detection of setup and hold time violation in the input resisters of bi-directional pins". Depending on this flag, the check is or isn't performed. I reviewed the code in the Cyclone II (Vital) models, and there is indeed a flag CheckInfo.Violation. How is it possible to disable setup and hold time checks during simulation? When they happen, the related signals become undefined 'X', thus compromising the rest of the gate simulation in Modelsim (Cyclone II models, from Quartus II). I am designing a special measuring circuit in which setup and hold times of FF are sometimes violated.
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